The present invention relates to an error correction control system for a control memory in a microprogram-controlled data processor.
In a microprogram-controlled data processor, a plurality of microinstructions stored in a high-speed control memory are sequentially read out to a microinstruction register and then supplied to and decoded in an arithmetic circuit, thereby executing a software instruction. Each microinstruction consists of a plurality of fields containing next address information, an error correction code, and the like in addition to an operation code and data.
In a conventional error correction control system for a control memory, a correctable error is detected for all the fields of the microinstruction. In a clock cycle in which an error is detected, updating of the microinstruction register is inhibited and at the same time an operation of the arithmetic circuit is inhibited.
In general, however, since the arithmetic circuit is physically separated away from the control memory, a time required for an operation inhibit signal to reach the arithmetic circuit is increased. Therefore, a cycle or period of a clock of the microprogram-controlled data processor is undesirably limited.